Application of a TDDB Model to the Optimization of the Programming Voltage and Dimensions of Antifuse Bitcells

Author

Deloge, Matthieu ; Allard, Bruno ; Candelier, Philippe ; Damiens, Joël ; Le-Roux, Elise ; Rafik, Mustapha

Author_Institution

CCDS/Fuse Solutions, Ampere & STMicroelectronics, Crolles, France

Volume

32

Issue

8

fYear

2011

Firstpage

1041

Lastpage

1043

Abstract

The optimization of the programming voltage and the dimensions of antifuse bitcells is a design challenge due to antagonistic parameters. An optimization approach is presented using a time-dependent dielectric breakdown (TDDB) model. Fowler-Nordheim wear-out current and T_BD power-law models are identified using electrical characterizations performed on antifuse bitcells fabricated in standard 40-nm CMOS. The TDDB model allows the calculation of the programming voltage according to a targeted T_BD and the antifuse bitcell dimensions. As a result, it was shown that the lowest programming voltage is obtained for a small capacitor, whereas the size of the drift transistor has a second-order impact.

Keywords

CMOS memory circuits; capacitors; electric breakdown; optimisation; random-access storage; CMOS integrated circuit; Fowler-Nordheim wear-out current; TBD power-law; TDDB model; antagonistic parameters; antifuse bitcell dimensions; drift transistor; optimization; programming voltage; size 40 nm; small capacitor; time-dependent dielectric breakdown; Capacitors; Electric breakdown; Logic gates; Mathematical model; Programming; Transistors; Voltage measurement; Antifuse; TDDB modeling; dielectric breakdown; nonvolatile memory;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2158054

Filename

5930322