Title :
Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI
Author :
Mastrapasqua, Marco ; Palestri, P. ; Pacelli, Andrea ; Celler, George K. ; Frei, M.R. ; Smith, P.R. ; Johnson, R.W. ; Bizzarro, L. ; Lin, W. ; Ivanov, Tony G. ; Carroll, Michael S. ; Kizilyalli, Isik C. ; King, C.A.
Author_Institution :
Agere Syst., Murray Hill, NJ, USA
fDate :
3/1/2002 12:00:00 AM
Abstract :
We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region underneath results in a very low collector-to-substrate capacitance. We also show that this process option achieves a much lower thermal resistance than using SOI with deep trench isolation, both reducing cost and curbing self-heating effects.
Keywords :
BiCMOS integrated circuits; Ge-Si alloys; buried layers; capacitance; ion implantation; isolation technology; semiconductor materials; silicon-on-insulator; thermal resistance; 0.25 micron; SOI; Si; SiGe BiCMOS; buried oxide layer; collector-to-substrate capacitance; floating n-type region; high-energy implant; high-performance implementation; low fabrication cost implementation; self-heating effects reduction; thermal resistance minimisation; BiCMOS integrated circuits; Capacitance; Costs; Fabrication; Germanium silicon alloys; Implants; Lithography; Silicon germanium; Thermal conductivity; Thermal resistance;
Journal_Title :
Electron Device Letters, IEEE
