Title :
A 0.31–1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications
Author :
Young-Jae Min ; Chan-Hui Jeong ; Kyu-Young Kim ; Won Ho Choi ; Jong-Pil Son ; Chulwoo Kim ; Soo-won Kim
Author_Institution :
Sch. of Electr. Eng., Korea Univ., Seoul, South Korea
Abstract :
This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm2. The measured duty-cycle error for the 50% duty-rate is below 1% (or 10 pS) within 320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.
Keywords :
CMOS integrated circuits; DRAM chips; detector circuits; search problems; CMOS process; DCC circuit; DDR DRAM applications; SAR-controller; binary search algorithm; duty cycle corrector; duty-correction controller; duty-cycle adjuster; duty-cycle controller; duty-cycle detector; duty-cycle output buffer; external input duty-cycle error; fast-corrected duty-cycle corrector; frequency 0.31 GHz to 1 GHz; frequency 312.5 MHz to 1 GHz; output signal; power 3.2 mW; size 0.13 mum; successive approximation register; Clocks; Delay lines; Detectors; Generators; Random access memory; Registers; Solid state circuits; DRAM; Double data rate (DDR); duty-cycle corrector (DCC); successive approximation register (SAR) controller;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2011.2158011
