A 650-MHz, IA-32 microprocessor with enhanced data streaming for graphics and video

Author

Senthinathan, Ramesh ; Fischer, Stephen ; Rangchi, Hamid ; Yazdanmehr, Hadi

Author_Institution

Microprocessor Products Group, Intel Corp., Folsom, CA, USA

Volume

34

Issue

11

fYear

1999

fDate

11/1/1999 12:00:00 AM

Firstpage

1454

Lastpage

1465

Abstract

This paper describes a new IA-32 architecture microprocessor that implements 70 additional instructions to further accelerate the performance of data-streaming applications such as three-dimensional graphics and video encode/decode. This processor is an enhancement over the previous implementation of this family through the addition of these new instructions along with circuit improvements in several key areas for higher clock frequency. The 10.17×12.10 mm² die contains 9.5 million transistors and is fabricated in a CMOS five-layer-metal 0.25-μm process with a six-layer organic land grid array package using C4 interconnect technology. It has an operating range of 1.4-2.2 V and is currently running up to 650 MHz

Keywords

CMOS digital integrated circuits; computer graphic equipment; data compression; digital signal processing chips; integrated circuit packaging; microprocessor chips; parallel architectures; video coding; 0.25 micron; 1.4 to 2.2 V; 3D graphics; 650 MHz; C4 interconnect technology; CMOS five-layer-metal process; DSP chip; IA-32 microprocessor; SIMD architecture; data-streaming applications; land grid array package; three-dimensional graphics; video decoding; video encoding; Acceleration; CMOS process; Circuits; Clocks; Decoding; Frequency; Graphics; Microprocessors; Packaging; Streaming media;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.799850

Filename

799850