A seventh-generation x86 microprocessor

Author

Golden, Michael ; Hesley, Steve ; Scherer, Alisa ; Crowley, Matthew ; Johnson, Scott C. ; Meier, Stephan ; Meyer, Dirk ; Moench, Jerry D. ; Oberman, Stuart ; Partovi, Hamid ; Weber, Fred ; White, Scott ; Wood, Tim ; Yong, John

Author_Institution

Adv. Micro Devices Inc., Sunnyvale, CA, USA

Volume

34

Issue

11

fYear

1999

fDate

11/1/1999 12:00:00 AM

Firstpage

1466

Lastpage

1477

Abstract

An out-of-order, three-way superscalar ×86 microprocessor with a 15-stage pipeline, organized to allow 600 MHz operation, can fetch, decode, and retire up to three ×86 instructions per cycle to independent integer and floating-point schedulers. The schedulers can simultaneously dispatch up to nine operations to seven integer and three floating-point execution resources. A sophisticated, cell-based design technique and judicious application of custom circuitry permit the development of a processor with an aggressive architecture and high clock frequency with a rapid design cycle. Design-for-test techniques such as scan and clock bypassing permit straightforward testing and debugging of the part

Keywords

clocks; design for testability; floating point arithmetic; microprocessor chips; pipeline processing; 600 MHz; cell-based design technique; clock bypassing; clock frequency; custom circuitry; design-for-test techniques; floating-point schedulers; integer schedulers; multi-stage pipeline; rapid design cycle; seventh-generation x86 microprocessor; three-way superscalar microprocessor; Circuit testing; Clocks; Debugging; Decoding; Design for testability; Frequency; Microprocessors; Out of order; Pipelines; Processor scheduling;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.799851

Filename

799851