A seventh-generation x86 microprocessor

An out-of-order, three-way superscalar ×86 microprocessor with a 15-stage pipeline, organized to allow 600 MHz operation, can fetch, decode, and retire up to three ×86 instructions per cycle to independent integer and floating-point schedulers. The schedulers can simultaneously dispatch up to nine operations to seven integer and three floating-point execution resources. A sophisticated, cell-based design technique and judicious application of custom circuitry permit the development of a processor with an aggressive architecture and high clock frequency with a rapid design cycle. Design-for-test techniques such as scan and clock bypassing permit straightforward testing and debugging of the part