Title :
An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode
Author :
Mizuno, Hiroyuki ; Ishibashi, Koichiro ; Shimura, Takanori ; Hattori, Toshihiro ; Narita, Susumu ; Shiozawa, Kenji ; Ikeda, Shuji ; Uchiyama, Kunio
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
11/1/1999 12:00:00 AM
Abstract :
A low-standby-current 1.8-V, 200-MHz microprocessor has been fabricated with a 0.2-μm, five-metal, dual-oxide-thickness, CMOS technology and two power down modes (i.e., a standby mode and a data-retention mode). The microprocessor uses a switched substrate-impedance scheme to bias substrates in the standby mode while maintaining a 200-MHz operating speed. Data-retention capability during the standby mode is also maintained. This mode achieves 46.5-μA standby current. The microprocessor also offers a battery-backup capability in a self-substrate-biased data-retention mode. This makes it possible to apply a deep substrate bias without increasing the gate-induced drain leakage current or p-n junction current. The current consumption is only 17.8 μA when operating off a 1-V supply in the data-retention mode
Keywords :
CMOS digital integrated circuits; leakage currents; low-power electronics; microprocessor chips; 0.2 micron; 1 to 1.8 V; 17.8 to 18 muA; 200 MHz; 46.5 muA; CMOS technology; LV microprocessor; battery-backup capability; low-standby-current; power down modes; self-substrate-biased data-retention mode; switched substrate-impedance scheme; CMOS technology; Degradation; Integrated circuit noise; Leakage current; MOSFETs; Microprocessors; Semiconductor device noise; Substrates; Subthreshold current; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
