Title :
A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm, 3.5-nm Tox, 1.8-V CMOS technology
Author :
Sanchez, Hector Eloys ; Sigel, J. ; Nicoletta, Carmine ; Nissen, James P. ; Alvarez, Josée
Author_Institution :
Somerset Design Center, Motorola Inc., Austin, TX, USA
fDate :
11/1/1999 12:00:00 AM
Abstract :
This I/O driver supports 3.3/2.5/1.8-V interfaces in a 3.5-nm Tox, 1.8-V CMOS technology. A bias generator, its switch capacitors, and a level shifter with protection network guarantee reliability and improve noise rejection. Measured output timing degradation is 2.5 ps per I/O switching. Buried resistors limit variation in output impedance. Interface delay of 2 ns with worst case I/O switching allows 400-MHz operation
Keywords :
CMOS digital integrated circuits; driver circuits; high-speed integrated circuits; integrated circuit noise; integrated circuit reliability; protection; 0.2 micron; 1.8 to 3.3 V; 3.5 nm; 400 MHz; CMOS I/O driver; bias generator; high speed bus; level shifter; noise rejection; protection network; reliability; switch capacitors; CMOS technology; Degradation; Impedance; Noise generators; Noise level; Protection; Resistors; Switched capacitor networks; Switches; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
