Title :
110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock
Author :
Takahashi, Toshiro ; Muto, Takashi ; Shirai, Yuji ; Shirotori, Fumihiko ; Takada, Yoshifumi ; Yamagiwa, Akira ; Nishida, Akira ; Hotta, Atsuo ; Kiyuna, Tadashi
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
fDate :
11/1/1999 12:00:00 AM
Abstract :
A simultaneous bidirectional transceiver logic (SBTL), for a 0.25 μm CMOS embedded array, has a low-voltage-swing input flip-flop circuit and an output flip-flop with a boundary scan to enable a 1.1-Gb/s data transfer per LSI pin with a 550-MHz system clock. Clock skew and jitter minimization enables high bandwidth in a phase-locked system. Measured latency time for transmission is less than 3.0 ns during simultaneous switching mode when the cable length is 18 cm. Average power consumption is 12 mW per pin at 550 MHz. A low-noise output buffer and a controlled collapse chip connection (C4)-based 1595-pin package with on-package capacitors achieve 100-byte data bus. The maximum data bandwidth per LSI is 110 GB/s
Keywords :
CMOS logic circuits; application specific integrated circuits; digital phase locked loops; flip-flops; high-speed integrated circuits; integrated circuit noise; large scale integration; logic arrays; synchronisation; timing; timing jitter; 0.25 micron; 1.1 Gbit/s; 100 to 110 GB/s; 12 mW; 3 ns; 550 MHz; ASIC; C4-based package; CMOS embedded array; LSI; SBTL; boundary scan flip flop; clock skew minimization; controlled collapse chip connection; jitter minimization; low-noise output buffer; low-voltage-swing input flip-flop circuit; onpackage capacitors; phase-locked system; simultaneous bidirectional transceiver logic; simultaneous switching mode; system clock; Bandwidth; CMOS logic circuits; Clocks; Flip-flops; Jitter; Large scale integration; Logic arrays; Minimization; Synchronization; Transceivers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
