Title :
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism
Author :
Kubosawa, Hajime ; Higaki, Naoshi ; Ando, Satoshi ; Takahashi, Hiromasa ; Asada, Yoshimi ; Anbutsu, Hideaki ; Sato, Tomio ; Sakate, Masato ; Suga, Atsuhiro ; Kimura, Michihide ; Miyake, Hideo ; Okano, Hiroshi ; Asato, Akira ; Kimura, Yasunori ; Nakayama,
Author_Institution :
Syst. LSI Dev. Labs., Fujitsu Labs. Ltd., Kawasaki, Japan
fDate :
11/1/1999 12:00:00 AM
Abstract :
A four-way very long instruction word (VLIW), 312-MHz geometry processor with peripheral component interconnect/accelerated graphic port bus bridge was implemented in a 0.21-μm, 2.5-V, three-layer-metal CMOS process. We adopted (1) a software bypass mechanism, (2) single-instruction multiple-data stream instructions, (3) four sets of floating-point multiply add and accumulate execution units, (4) special condition code registers and a branch condition generator for a clipping operation, and (5) automatic clock delay tuning methodology. As a result of these features, we achieved a performance of 2.5 GFLOPS and 6.5 million polygons per second for a three-dimensional geometry processor, which is the highest published performance as a single geometry processor. The processor is applicable to computer-aided-design systems that require very high graphics performance
Keywords :
CMOS digital integrated circuits; computer graphic equipment; engineering graphics; floating point arithmetic; instruction sets; microprocessor chips; parallel architectures; pipeline arithmetic; solid modelling; 0.21 micron; 2.5 GFLOPS; 2.5 V; 312 MHz; 3D geometry processor; CAD systems; SIMD instructions; accelerated graphic port bus bridge; automatic clock delay tuning methodology; branch condition generator; clipping operation; computer-aided-design systems; floating-point multiply add/accumulate execution units; four-way VLIW geometry processor; peripheral component interconnect; single-instruction multiple-data; software bypass mechanism; special condition code registers; three-layer-metal CMOS process; very long instruction word; Acceleration; Bridges; CMOS process; Clocks; Delay; Geometry; Graphics; High performance computing; Registers; VLIW;
Journal_Title :
Solid-State Circuits, IEEE Journal of
