Title :
A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure
Author :
Aoki, Masakazu ; Nakagome, Yoshinobu ; Horiguchi, Masashi ; Tanaka, Hitoshi ; Ikenaga, Shin Ichi ; Etoh, Jun ; Kawamoto, Yoshifumi ; Kimura, Shin Ichiro ; Takeda, Eiji ; Sunami, Hideo ; Itoh, Kiyoo
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fDate :
10/1/1988 12:00:00 AM
Abstract :
Low-noise, high-speed circuit techniques for high-density DRAMs (dynamic random-access memories), as well as their application to a single 5-V 16-Mb CMOS DRAM with a 3.3-V internal operating voltage for a memory array, are described. It was found that data-line interference noise becomes unacceptably high (more than 25% of the signal) and causes a serious problem in 16-Mb DRAM memory arrays. A transposed data-line structure is proposed to eliminate the noise. Noise suppression below 5% is confirmed using this transposed data-line structure. A current sense amplifier is also proposed to maintain the data-transmission speed in common I/O lines, in spite of a reduced operating voltage and increased parasitic capacitance loading in the memory array. A speed improvement of 10 ns is achieved. Using these circuit techniques, a 16-Mb CMOS DRAM with a typical RAS access time of 60 ns was realized
Keywords :
CMOS integrated circuits; integrated memory circuits; random-access storage; 16 Mbit; 3.3 V; 5 V; 60 ns; CMOS DRAM; RAS access time; current sense amplifier; dynamic RAM; dynamic random-access memories; high-density; high-speed circuit techniques; internal operating voltage; low noise device; memory array; noise suppression; single supply voltage; transposed data-line structure; CMOS memory circuits; CMOS technology; Circuit noise; Interference; Noise generators; Parasitic capacitance; Power generation; Random access memory; Signal generators; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
