The impact of data-line interference noise on DRAM scaling

A kind of data-line (DL) interference noise in a scaled DRAM cell array is found and studied through analysis. The dynamic behavior of cell arrays due to sense-amplifier operation is derived analytically. Analysis shows that the amount of interference noise is more than three times larger than expected from simple data-line coupling. A novel experimental technique for precise noise determination is developed to verify the analysis. Analytical results are in good agreement with the experimental data. It is found that the interference noise plays a dominant role in determining the operating margin of the DRAM and that a novel process or a cell array architecture for minimizing the interference noise is indispensable in 16-Mb DRAM and beyond