Title :
A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM´s
Author :
Kawahara, Takayuki ; Kawajiri, Yoshiki ; Kitsukawa, Goro ; Nakagome, Yoshinobu ; Sagara, Kazuhiko ; Kawamoto, Yoshifumi ; Akiba, Takesada ; Kato, Shisei ; Kawase, Yasushi ; Itoh, Kiyoo
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fDate :
11/1/1991 12:00:00 AM
Abstract :
The feasibility of realizing an emitter-coupled-logic (ECL) interface 4-Mb dynamic RAM (DRAM) with an access time under 10 ns using 0.3-μm technology is explored, and a deep submicrometer BiCMOS VLSI using this technology is proposed. Five aspects of such a DRAM are covered. They are the internal power supply voltage scheme using on-chip voltage limiters, an ECL DRAM address buffer with a reset function and level converter, a current source for address buffers compensated for device parameter fluctuation, an overdrive rewrite amplifier for realizing a fast cycle time, and double-stage current sensing for the main amplifier and output buffer. Using these circuit techniques, an access time of 7.8 ns is expected with a supply current of 198 mA at a 16-ns cycle time
Keywords :
BIMOS integrated circuits; DRAM chips; VLSI; emitter-coupled logic; 0.3 micron; 10 ns; 16 ns; 198 mA; 4 Mbit; 7.8 ns; BiCMOS; ECL DRAM; ECL interface; VLSI; access time; address buffer; current source; cycle time; deep submicrometer; double-stage current sensing; dynamic RAM; emitter-coupled-logic; internal power supply voltage scheme; level converter; on-chip voltage limiters; overdrive rewrite amplifier; reset function; BiCMOS integrated circuits; CMOS technology; Current supplies; Fluctuations; Helium; Power amplifiers; Power supplies; Random access memory; System performance; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
