A 17-ns 4-Mb CMOS DRAM

Author

Nagai, Takeshi ; Numata, Kenji ; Ogihara, Masaki ; Shimizu, Mitsuru ; Imai, Kimimasa ; Hara, Takahiko ; Yoshida, Munehiro ; Saito, Yoshikazu ; Asao, Yoshiaki ; Sawada, Shizuo ; Fujii, Syuso

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

26

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1538

Lastpage

1543

Abstract

A 17-ns nonaddress-multiplexed 4-Mb dynamic RAM (DRAM) fabricated with a pure CMOS process is described. The speed limitations of the conventional DRAM sensing technique are discussed, and the advantages of using the direct bit-line sensing technique are explained. A direct bit-line sensing technique with a two-stage amplifier is described. One readout amplifier is composed of a two-stage current-mirror amplifier and a selected readout amplifier is activated by a column decoder output before the selected word line rises. The amplifier then detects a small bit-line signal appearing on a bit-line pair immediately after the word-line rise. This two-stage amplification scheme is essential to improving access time, especially in the case of a CMOS process. The high sensitivity of the readout amplifier is discussed, and the electrical features and characteristics of the fabricated DRAM are reported

Keywords

CMOS integrated circuits; DRAM chips; 17 ns; 4 Mbit; CMOS DRAM; access time; column decoder output; current-mirror amplifier; direct bit-line sensing; dynamic RAM; nonaddress-multiplexed; readout amplifier; two-stage amplifier; BiCMOS integrated circuits; CMOS process; CMOS technology; Decoding; Helium; Microprocessors; Random access memory; Read-write memory; Semiconductor device measurement; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.98969

Filename

98969