Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test

Author

Horiguchi, Masashi ; Aoki, Masakazu ; Etoh, Jun ; Itoh, Kiyoo ; Kajigaya, Kazuhiko ; Nozoe, Atsushi ; Matsumoto, Tetsurou

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

26

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1544

Lastpage

1549

Abstract

The authors present a dynamic RAM (DRAM) voltage limiter with a burn-in test mode. It features a dual-regulator dual-trimmer scheme that provides a precise stress voltage in a burn-in test while maintaining a constant limited voltage under normal operation. A regulator is used to preserve a constant difference between the internal burn-in voltage and the supply voltage. Two sets of trimmers reduce the voltage deviations of both the burn-in and normal-operation voltages within ±0.13 V. The circuits are implemented in a 16-Mb CMOS DRAM. A burn-in voltage regulated to ±50 mV at an ambient temperature up to 120°C is obtained simply by elevating the supply voltage to 8 V as in conventional burn-in procedures

Keywords

CMOS integrated circuits; DRAM chips; decoding; integrated circuit testing; limiters; voltage regulators; 120 degC; 16 Mbit; 50 mV; 8 V; CMOS; DRAM; burn-in test; dual-decoding-trimmer; dual-regulator; dynamic RAM; memory IC; stress voltage; voltage limiter; Circuit testing; Large scale integration; Power supplies; Power system reliability; Random access memory; Regulators; Stress; Temperature; Threshold voltage; Variable structure systems;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.98970

Filename

98970