A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

Author

Chappell, Terry I. ; Chappell, Barbara A. ; Schuster, Stanley E. ; Allan, James W. ; Klepner, Stephen P. ; Joshi, Rajiv V. ; Franch, Robert L.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

26

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1577

Lastpage

1585

Abstract

The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined

Keywords

CMOS integrated circuits; SRAM chips; emitter-coupled logic; pipeline processing; 2 ns; 3.8 ns; 512 kbit; CMOS; ECL SRAM; access time; cycle time; emitter-coupled-logic; fully pipelined architecture; static RAM; wire RC delays; Circuits; Costs; Degradation; Pipeline processing; Power supplies; Random access memory; Resistors; Robustness; Switches; Thin film transistors;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.98975

Filename

98975