A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

Author

Nakayama, Takeshi ; Kobayashi, Shin-ichi ; Miyawaki, Yoshikazu ; Terada, Yasushi ; Ajika, Natsuo ; Ohi, Makoto ; Arima, Hideaki ; Matsukawa, Takayuki ; Yoshihara, Tsutomu ; Suzuki, Kimio

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

Volume

26

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1600

Lastpage

1605

Abstract

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks, in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm×2.0 μm and a chip size of 6.5 mm×18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process

Keywords

CMOS integrated circuits; EPROM; PLD programming; integrated memory circuits; 0.6 micron; 16 Mbit; 60 ns; CMOS process; access time; differential sensing scheme; dummy cells; erase pulse application; erase sequence controller; erase-verify operation; flash EEPROM; memory array; on-chip oscillator; program control system; stacked gate cell structure; synchronous circuit; Aluminum; CMOS process; Circuits; Control systems; EPROM; Energy consumption; Hard disks; Manufacturing processes; Random access memory; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.98978

Filename

98978