Title :
A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates
Author :
Notomi, Seishi ; Watanabe, Yuu ; Kosugi, Makoto ; Hanyu, Isamu ; Suzuki, Masahisa ; Mimura, Takashi ; Abe, Masayuki
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
fDate :
11/1/1991 12:00:00 AM
Abstract :
A 45 K-gate emitter-coupled-logic (ECL)-compatible array with unbuffered and buffered direct-coupled FET-logic (DCFL and BDCFL) gates has been developed using 0.6-μm-gate high-electron-mobility transistors (HEMTs) and four-level gold-based interconnects. The high-speed DCFL gates and more functional BDCFL gates are used to replace ECL macros efficiently. The basic cell, equivalent to four three-input NOR gates, consists of 12 enhancement-mode (E-mode) HEMTs, four depletion mode (D-mode) HEMTs, and two source-follower buffers. The basic gate delay times are 35 ps for 0.24-mW unbuffered DCFL gates and 50 ps for 0.38-mW BDCFL gates. The gate array chip is 9.8×9.8 mm and contains 45600 gates. The chip dissipates 11 W in 80% gate use. Silylated polymethyl silsequioxane (PMSS), which has a low dielectric constant of 3, is used for the interlayer dielectrics to reduce wiring delay
Keywords :
VLSI; field effect integrated circuits; high electron mobility transistors; logic arrays; 0.24 mW; 0.38 mW; 0.6 micron; 11 W; 35 ps; 50 ps; 9.8 mm; BDCFL gates; D-mode HEMTs; DCFL gates; E-mode HEMTs; ECL compatible; HEMT array; PMSS; buffered DCFL; direct-coupled FET-logic; four level metallisation; gate array chip; gate arrays; gate delay times; interlayer dielectrics; low permittivity dielectrics; silylated polymethyl silsequioxane; unbuffered DCFL; Delay; Dielectric constant; Fabrication; Gallium arsenide; HEMTs; Integrated circuit interconnections; Inverters; Logic arrays; Logic circuits; MODFETs;
Journal_Title :
Solid-State Circuits, IEEE Journal of
