Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAM

Author

Horiguchi, Masashi ; Aoki, Masakazu ; Tanaka, Hitoshi ; Etoh, Jun ; Nakagome, Yoshinobu ; Ikenaga, Shin´Ichi ; Kawamoto, Yoshifumi ; Itoh, Kiyoo

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

23

Issue

5

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1128

Lastpage

1132

Abstract

A dual-operating-voltage scheme (5 V for peripheral circuits and 3.3 V for the memory array) is shown to be the best approach for a single 5-V 16-Mb DRAM (dynamic random-access memory). This is because the conventional scaling rule cannot apply to DRAM design due to the inherent DRAM word-line boosting feature. A novel internal voltage generator to realize this approach is presented. Its features are the switching of two reference voltages, a driver using a PMOS-load differential amplifier, and the word-line boost based on the regulated voltage, which can ensure a wider memory margin than conventional circuits. This approach is applied to an experimental 16-Mb DRAM. A 0.5% supply-voltage dependency and 30-ns recovery time are achieved

Keywords

CMOS integrated circuits; driver circuits; integrated memory circuits; random-access storage; voltage regulators; 16 Mbit; 3.3 V; 30 ns; 5 V; CMOS IC; DRAM; PMOS-load differential amplifier; driver; dual-operating-voltage scheme; dynamic RAM; dynamic random-access memory; internal voltage generator; memory array; peripheral circuits; recovery time; single supply voltage; Boosting; Capacitors; Differential amplifiers; Driver circuits; Maintenance; Power dissipation; Power supplies; Random access memory; Switching circuits; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.5934

Filename

5934