Quasi-complementary BiCMOS for sub-3-V digital circuits

Author

Yano, Kazuo ; Hiraki, Mitsuru ; Shukuri, Shoji ; Onose, Yasuo ; Hirao, Mitsuru ; Ohki, Nagatoshi ; Nishida, Takashi ; Seki, Koichi ; Shimohigashi, Katsuhiro

Author_Institution

Center for Solid State Electron. Res., Arizona State Univ., Tempe, AZ, USA

Volume

26

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1708

Lastpage

1719

Abstract

The authors describe a quasi-complementary BiCMOS (QC-BiCMOS) circuit scheme for the low-supply-voltage deep-submicrometer regime. A QC-BiCMOS performs twice as fast as a CMOS even at a 2.5-V supply without a p-n-p bipolar transistor. Key circuits for this low-voltage performance are a separation between the base of the pull-up bipolar and the base of a quasi-p-n-p and the carefully designed base discharging circuit. A quasi-p-n-p combination of a pMOS and an n-p-n bipolar based on these circuits shows an equivalent cutoff frequency of over 10 GHz. The delay expressions for the QC-BiCMOS are analyzed and compared with the conventional BiCMOS. A 0.3-μm fully loaded three-input NAND gate was fabricated, verifying that the QC-BiCMOS has more than twice the performance leverage over the conventional BiCMOS and the CMOS at a sub-3-V supply

Keywords

BIMOS integrated circuits; NAND circuits; VLSI; digital integrated circuits; integrated circuit technology; logic gates; 0.3 micron; 10 GHz; 3 to 2.5 V; QC-BiCMOS; base discharging circuit; cutoff frequency; deep-submicrometer regime; delay expressions; low-supply-voltage; performance; quasi-complementary BiCMOS; sub-3-V digital circuits; three-input NAND gate; BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Cutoff frequency; Degradation; Delay effects; Digital circuits; Laboratories; Low voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.98993

Filename

98993