Title :
A 128 K×8 70-MHz multiport video RAM with auto register reload and 8×4 block WRITE feature
Author :
Pinkham, R. ; Russell, D. ; Balistreri, Anthony ; Herndon, Troy H. ; Anderson, Daniel ; Mehta, Aswin ; Nguyen, Thanh ; Hong, Ngai Hung ; Sakurai, Hiroshi ; Hatakoshi, Seishi ; Guillemaud, Andandre
Author_Institution :
Texas Instrum. Inc., Houston, TX, USA
fDate :
10/1/1988 12:00:00 AM
Abstract :
An 80-ns 1-Mb multiport video random-access memory (VRAM) can be organized as 128 K×8 or 256 K×4. Uninterrupted serial data streams of 70 MHz are achieved by combining pipelining and interleaving techniques with an internally triggered automatic memory-to-register transfer mechanism. DRAM bandwidth is enhanced by a block WRITE feature which can write as many as four column address locations in every CAS cycle. The write-per-bit feature has been expanded by including an on-chip write-per-bit latch and an extended mode of operation to simplify its use in a wider range of systems. The VRAM is fabricated in a 1 μm CMOS technology using double-level poly/polycide, single level metal, and trench DRAM storage capacitors for high noise immunity
Keywords :
CMOS integrated circuits; integrated memory circuits; pipeline processing; random-access storage; 1 Mbit; 1 micron; 70 MHz; 80 ns; CMOS technology; VRAM; auto register reload; automatic memory-to-register transfer mechanism; block WRITE feature; double-level poly/polycide; interleaving techniques; internally triggered transfer mechanism; multiport video RAM; on-chip write-per-bit latch; pipelining; random-access memory; serial data streams; single level metal; trench DRAM storage capacitors; Bandwidth; CMOS technology; Content addressable storage; Interleaved codes; Pipeline processing; Random access memory; Read-write memory; Registers; Streaming media; System-on-a-chip;
Journal_Title :
Solid-State Circuits, IEEE Journal of
