DocumentCode :
1262853
Title :
Hierarchical Thermal Management Policy for High-Performance 3D Systems With Liquid Cooling
Author :
Zanini, Francesco ; Sabry, Mohamed M. ; Atienza, David ; De Micheli, Giovanni
Author_Institution :
Lab. of Integrated Syst. (LSII), Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland
Volume :
1
Issue :
2
fYear :
2011
fDate :
6/1/2011 12:00:00 AM
Firstpage :
88
Lastpage :
101
Abstract :
Three-dimensional (3D) integrated circuits and systems are expected to be present in electronic products in the short term. We consider specifically 3D multi-processor systems-on-chips (MPSoCs), realized by stacking silicon CMOS chips and interconnecting them by means of through-silicon vias (TSVs). Because of the high power density of devices and interconnect in the 3D stack, thermal issues pose critical challenges, such as hot-spot avoidance and thermal gradient reduction. Thermal management is achieved by a combination of active control of on-chip switching rates as well as active interlayer cooling with pressurized fluids. In this paper, we propose a novel online thermal management policy for high-performance 3D systems with liquid cooling. Our proposed controller uses a hierarchical approach with a global controller regulating the active cooling and local controllers (on each layer) performing dynamic voltage and frequency scaling (DVFS) and interacting with the global controller. Then, the on-line control is achieved by policies that are computed off-line by solving an optimization problem that considers the thermal profile of 3D-MPSoCs, its evolution over time and current time-varying workload requirements. The proposed hierarchical scheme is scalable to complex (and heterogeneous) 3D chip stacks. We perform experiments on a 3D-MPSoC case study with different interlayer cooling structures, using benchmarks ranging from web-accessing to playing multimedia. Results show significant advantages in terms of energy savings that reaches values up to 50% versus state-of-the-art thermal control techniques for liquid cooling, and thermal balance with differences of less than 10°C per layer.
Keywords :
CMOS digital integrated circuits; cooling; elemental semiconductors; silicon; system-on-chip; thermal management (packaging); three-dimensional integrated circuits; 3D multi-processor systems-on-chips; MPSoC; TSV; current time-varying workload requirements; dynamic voltage frequency scaling; hierarchical thermal management; high-performance 3D systems; liquid cooling; stacking silicon CMOS chips; thermal gradient reduction; thermal profile; through-silicon vias; Heating; Liquid cooling; Mathematical model; Microchannel; Thermal management; Three dimensional displays; Hardware/software co-design; multilayer; multiprocessor system-on-chip (SoC); power modeling and estimation; thermal;
fLanguage :
English
Journal_Title :
Emerging and Selected Topics in Circuits and Systems, IEEE Journal on
Publisher :
ieee
ISSN :
2156-3357
Type :
jour
DOI :
10.1109/JETCAS.2011.2158272
Filename :
5936647
Link To Document :
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