Title :
An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution
Author :
Rhee, Woogeun ; Bisanti, Biagio ; Ali, Akbar
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
4/1/2002 12:00:00 AM
Abstract :
A 2.5-GHz/900-MHz dual fractional-N/integer-N frequency synthesizer is implemented in 0.35-μm 25-GHz BiCMOS. A ΔΣ fractional-N synthesizer is employed for RF channels to have agile switching, low in-band noise, and fine frequency resolution. Implementing two synthesizers with an on-chip ΔΣ modulator in a small package is challenging since the modulator induces substantial digital noise. In this work, several design aspects regarding noise coupling are considered. The fractional-N synthesizer offers less than 10-Hz frequency resolution having the in-band noise contribution of -88 dBc/Hz for 2.47-GHz output frequency and -98 dBc/Hz for 1.15-GHz output frequency, both measured at 20-kHz offset frequency. The prototype dual synthesizer consumes 18 mW with 2.6-V supply
Keywords :
BiCMOS analogue integrated circuits; UHF integrated circuits; delta-sigma modulation; frequency synthesizers; integrated circuit design; integrated circuit noise; ΔΣ fractional-N synthesizer; 0.35 micron; 2.5 GHz; 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer; 2.6 V; 900 MHz; RF carrier resolution; W-CDMA; agile switching; design aspects; digital noise; dual fractional-N/integer-N frequency synthesizer; fine frequency resolution; low in-band noise; noise coupling; offset frequency; on-chip voltage regulator; output frequency; Bandwidth; BiCMOS integrated circuits; Channel spacing; Digital modulation; Frequency synthesizers; Integrated circuit synthesis; Packaging; Phase locked loops; Radio frequency; Radiofrequency integrated circuits;
Journal_Title :
Solid-State Circuits, IEEE Journal of
