Layout Scaling of $\hbox {Si}_{1-x}\hbox {Ge}_{x}\hbox {-Chan\nel}$ pFETs

Through a combination of electrical measurements, technology computer-aided design simulations, and wafer bending experiments, the effect of elastic stress relaxation on the layout dependence of Si_1-xGe_x-channel p-channel field-effect transistors (pFETs) is studied. This work focuses on scaling of the transistor width W, the active-area length (length of diffusion, LOD) for isolated transistors, and poly-to-poly length L_P/P of nested configurations. A strong narrow-width current enhancement is reported, even for relatively large widths, above 100 nm. On the other hand, the layout dependence on LOD or L_P/P is also predicted but only for aggressively scaled layouts (LOD or L_P/P below 100 nm). W and L_P/P scaling lead to current enhancement, whereas LOD scaling is expected to degrade performance. No significant dependence of short-channel threshold voltage on W, LOD, or L_P/P was observed. This study indicates that, as higher germanium concentrations of the channel lead to more layout dependence, this concentration may need to be optimized carefully to combine high channel mobility with limited added design complexity. Moreover, the channel thickness should be kept as thin as possible, as layout dependence is enhanced for thicker channels.