Title :
Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs
Author :
Song, Jun-Yong ; Kwon, Oh-Kyong
Author_Institution :
Dept. of Electron. & Comput. Eng., Hanyang Univ., Seoul, South Korea
fDate :
7/1/2011 12:00:00 AM
Abstract :
An independently controlled eye-tracking clock- and data-recovery (CDR) circuit that achieves enhanced high-frequency jitter tolerance is presented in this brief. In the proposed CDR, a data-tracking loop compensates interchannel timing skews and rejects low-frequency jitter of the data, and an eye-tracking loop tracks asymmetric jitter distribution and high-frequency jitter of the data to enhance high-frequency jitter tolerance. This can be achieved by independently controlling two loops in the digital domain. The CDR is implemented using an 0.18- μm CMOS process, and a bit error rate of less than 10-12 was achieved for a data rate up to 5.8 Gb/s using a 231 - 1 pseudorandom binary-sequence input.
Keywords :
CMOS memory circuits; DRAM chips; binary sequences; clock and data recovery circuits; error statistics; jitter; random sequences; synchronisation; CDR circuit; CMOS process; asymmetric jitter distribution; bit error rate; clock- and data-recovery circuit; data-tracking loop; digital domain; enhanced high-frequency jitter tolerance; high-speed graphic DRAM; independently controlled eye-tracking clock-recovery circuit; independently controlled eye-tracking loop; interchannel timing skews; low-frequency jitter; pseudorandom binary-sequence input; Bit error rate; Clocks; Decoding; Jitter; Phase locked loops; Random access memory; Tracking loops; Bang-bang phase detector (PD); clock and data recovery (CDR); complementary metal–oxide–semiconductor (CMOS); dynamic random access memory (DRAM); eye tracking; jitter tolerance;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2011.2158254
