Design of Multistandard Channelization Accelerators for Software Defined Radio Handsets

This paper presents a novel multistandard channelization accelerator design methodology for the digital front-end of a software defined radio (SDR) handset. Dedicated hardware (HW) accelerator cores have a power efficiency which is several orders higher than a software implementation and hence, have been extensively used for accelerating the computationally intensive tasks like channelization. However, these cores are generally inflexible and optimized for a single standard. The growing need for supporting multiple wireless standards with heterogeneous throughput and mobility requirements in a small form factor mobile handset with a limited silicon area, requires the accelerator cores to be flexible and reusable in addition to being power efficient. The proposed methodology exploits commonalities in the channelization specifications to hardwire and reuse a significant portion of the accelerator, across multiple standards. The resulting accelerator is area efficient and scalable for supporting an arbitrary number of standards.