Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits

Lowering supply voltage is still the most effective technique to reduce dynamic power, and Vdd is being pushed toward the threshold voltage for ultra-low power applications. However, near-threshold circuit leakage power is comparable to switching power and performance is highly sensitive to static and dynamic threshold voltage variations. This makes designing circuits for a target performance very difficult, and post-silicon tunability is required to achieve performance targets without taking huge design margins. Post-silicon tuning of voltage supply and body bias in active mode, together with power gating for idle leakage power minimization are being investigated to tackle variability challenges in near-threshold operation. In this paper, we review and put in perspective techniques recently proposed in the literature for fine-grained post-silicon tuning and power gating. These techniques leverage the typical row-based ASIC layout style and use the row as the atomic element for circuit clustering. The results of row-based power gating on a set of benchmark circuits show that the leakage savings can be achieved are, superior to those obtained using existing power-gating solutions and with much tighter timing and area constraints. Benchmark results on row-based forward body biasing show large leakage power savings with a maximum savings of 61% in case of 18% compensation in 45 nm and 93% in case of 10% compensation in 32 nm with respect to block-level approaches. Finally, row-based dual-Vdd can provide post-silicon speed compensation in near-threshold region up-to 45% while achieving more than 50% lower power compared to single-Vdd.