Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs

The design of complex systems-on-chip (SoCs) in the upcoming complementary metal-oxide-semiconductor (CMOS) technologies has become increasingly challenging due to the high levels of integration, the excessive energy consumption, the clock distribution problems and the increased process variability impact. To deal with these issues, we consider network-on-chip (NoC) architectures partitioned into several voltage-frequency domains and propose an efficient control algorithm for on-the-fly workload monitoring and management. This algorithm is able to cope with the technology-related variability and with the variable workload of the system. It dynamically controls the speed of the different voltage-frequency islands with respect to the process variability impact on each island. Within this work, a new clock synchronization scheme is also presented. Simulation results demonstrate the effectiveness of our approach in guarantying the average speed performance of the system under different cases of the process variability effect while keeping reduced the overall system energy consumption. Moreover, this is achieved with a small area overhead. The results are validated on a MIPS R2000 processor node using the 45 nm CMOS technology from STMicroelectronics.