43-ps 5.2-GHz macrocell array LSIs

Author

Suzuki, Masao ; Hirata, Michihiro ; Konaka, Shinsuke

Author_Institution

LSI Lab., NTT, Kanagawa, Japan

Volume

23

Issue

5

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1182

Lastpage

1188

Abstract

A family of bipolar macrocell array LSIs has been developed which has a basic delay of 43 ps/CML and a toggle frequency of 5.2 GHz/flip-flop. This family uses a cascaded-differential and single-ended CML circuit and a highly advanced super self-aligned process technology (SST-1B) which uses a selectively ion-implanted collector technology based on SST-1A. Using the macrocell array LSIs, performances of 1.2 ns/1.2 W for a 6-bit multiplier, and 4.3 ns/3 W for a 16-bit multiplier have been achieved

Keywords

bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; large scale integration; logic arrays; multiplying circuits; 1.2 W; 16-bit multiplier; 3 W; 43 ps; 5.2 GHz; 6-bit multiplier; CDS CML; ECL; SST-1B; advanced super self-aligned process technology; bipolar macrocell array LSIs; cascaded differential circuit; delay; family; selectively ion-implanted collector technology; single-ended CML circuit; toggle frequency; Adders; Communication switching; Delay; Digital communication; Flip-flops; Frequency; Large scale integration; Logic circuits; Macrocell networks; Silicon;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.5942

Filename

5942