DocumentCode :
1265873
Title :
Architectural energy optimization by bus splitting
Author :
Hsieh, Cheng-Ta ; Pedram, Massoud
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Volume :
21
Issue :
4
fYear :
2002
fDate :
4/1/2002 12:00:00 AM
Firstpage :
408
Lastpage :
414
Abstract :
This paper proposes split shared-bus architecture to reduce the energy dissipation for global data exchange among a set of interconnected modules. The bus splitting problem for minimum energy is formulated as a minimum-exchange bus split problem, which is shown to be NP-complete. The problem is solved heuristically by using a maximum-weight matching algorithm and combinatorial search. Experimental results show that the energy saving of split-bus architecture compared to monolithic-bus architecture varies from 16% to 50%, depending on the characteristics of the data transfer among the modules and the configuration of the split-bus. The proposed split-bus architecture can be extended to multiway split-bus architecture when large numbers of modules are to be connected
Keywords :
integrated circuit design; integrated circuit interconnections; low-power electronics; modules; network topology; NP-complete; architectural energy optimization; bus splitting; combinatorial search; data transfer; energy dissipation; global data exchange; interconnected modules; low-power design; maximum-weight matching algorithm; multiway architecture; split shared-bus architecture; Bandwidth; Energy consumption; Energy dissipation; Logic design; Microelectronics; Reconfigurable logic; Resource management; Signal design; Signal processing algorithms; System-on-a-chip;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.992764
Filename :
992764
Link To Document :
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