Title :
Correction to "Interconnect synthesis without wire tapering"
Author :
Alpert, Charles J. ; Devgan, A. ; Fishburn ; Quay, S.T.
Author_Institution :
IBM Austin Research Laboratory
fDate :
4/1/2002 12:00:00 AM
Keywords :
Design automation; Equations; Laboratories; Microelectronics; Wire;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2002.992775
