Low thermal-budget ultrathin NH/sub 3/-annealed atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics with excellent reliability

Author

Khosru, Quazi D M ; Nakajima, A. ; Yoshimoto, T. ; Yokoyama, S.

Author_Institution

Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan

Volume

23

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

179

Lastpage

181

Abstract

We present novel ultrathin (EOT = 2.1 nm) atomic-layer-deposited (ALD) Si-nitride/SiO/sub 2/ stack gate dielectrics annealed in NH/sub 3/ at a moderate temperature of 550/spl deg/C. MOS capacitors are fabricated using the proposed dielectrics. Excellent performance in electrical stressing experiments is shown by the dielectrics. They also exhibit better interface quality, low bulk-trap density, low trap generation rate, and high long-term reliability in comparison with ALD Si-nitride/SiO/sub 2/ stack dielectrics without NH/sub 3/-annealing and conventional thermal SiO/sub 2/ dielectrics. The proposed stack-gate dielectrics appear to be very promising for ULSI devices.

Keywords

MOS capacitors; annealing; dielectric thin films; electric breakdown; interface states; leakage currents; semiconductor device reliability; silicon compounds; vacuum deposition; 2.1 nm; 550 C; ALD; MOS capacitors; NH/sub 3/; NH/sub 3/ annealing; SiN-SiO/sub 2/; ULSI devices; atomic layer deposition; bulk-trap density; dielectric breakdown; electrical stressing experiments; equivalent oxide thickness; interface quality; leakage current; long-term reliability; low thermal-budget; trap generation rate; ultrathin SiN/SiO/sub 2/ stack gate dielectrics; ultrathin gate dielectrics; Annealing; Capacitance; Dielectric breakdown; Dielectric devices; Electric breakdown; Leakage current; MOS capacitors; Silicon; Temperature; Ultra large scale integration;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.992831

Filename

992831