The macro-modelling of logic functions for the SPICE simulator

The traditional method of using the SPICE simulator to evaluate logic functions includes a transistor-level representation of the function, resulting in very long simulation times. Macromodels, which use no semiconductor junctions, are proposed for the pure combinational logic functions, INVERT, AND, OR, NAND, NOR, XOR, and XNOR. A basic two-input topology is considered. In all cases, only one SPICE primitive performs the logic function. Thus, each gate can be readily expanded by adding input resistors, with virtually no speed penalty. A similar technique is applied to the construction of a macromodel of a digital-to-analog converter, yielding a topology of one SPICE primitive per converter, with no resistive networks, irrespective of the number of bits.<>