Title :
A wafer-scale 170000-gate FFT processor with built-in test circuits
Author :
Yamashita, Koichi ; Kanasugi, Akinori ; Hijiya, Shinpei ; Goto, Gensuke ; Matsumura, Nobutake ; Shirato, Takehide
Author_Institution :
Fujitsu Labs. Ltd., Atsugi, Japan
fDate :
4/1/1988 12:00:00 AM
Abstract :
The wafer-scale 170000-gate fast Fourier transform (FFT) processor described consists of individual repeatable building blocks, each of which contains a processing element (PE) and interconnection wiring. The PE consists of a multiplier accumulator and its built-in self-test circuits. The wafer system is reconfigured by connected active blocks after block self-diagnosis. Blocks are connected using a programmable contact-hole mask. The processor performs parallel 16-bit, eight-point complex FFTs and is implemented with 725 I/O pads in triple-metal 2.3-μm p-well CMOS technology on a 4-in. wafer. It is mounted by controlled-collapse bonding facedown on a 11.8×11.8-cm2 substrate
Keywords :
CMOS integrated circuits; VLSI; computerised signal processing; fast Fourier transforms; integrated circuit technology; microprocessor chips; parallel architectures; parallel machines; 11.8 cm; 16 bit; 2.3 micron; 4 in; ASIC; BIST; FFT processor; WSI; block self-diagnosis; built-in self-test circuits; built-in test circuits; controlled-collapse bonding; custom IC; eight-point complex FFTs; fast Fourier transform; interconnection wiring; microprocessors; multiplier accumulator; p-well CMOS technology; parallel processing; processing element; programmable contact-hole mask; repeatable building blocks; substrate; triple-metal; wafer scale integration; Built-in self-test; CMOS process; CMOS technology; Fast Fourier transforms; Flexible printed circuits; Integrated circuit interconnections; Logic devices; Logic testing; Packaging; Reconfigurable logic; Switches; System performance; System testing; Very large scale integration; Wafer bonding; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
