A 20-ns CMOS micro DSP core for video-signal processing

Author

Baji, Toru ; Kojima, Hirotsugu ; Ohba, Shinya ; Hayashida, Tetsuya ; Kaneko, Kenji ; Hagiwara, Yoshimune ; Sumi, Nario

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

23

Issue

5

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1203

Lastpage

1211

Abstract

A programmable 8-b digital signal processor core with an instruction cycle time of 20 ns is developed. A 37.5-mm chip is fabricated by advanced 1.0-μm double-level-metal CMOS technology. This processor has a reconfigurable high-speed data path supporting several multiply/accumulate function, including 16-tap linear-phase transversal filtering, high-speed adaptive filtering, and eight-point discrete cosine transformation. To provide high-speed operation within the chip, a programmable phase-locked loop circuit is built on the chip. This circuit generates a high-speed clock, which is a multiple of the system clock fed from outside, and is synchronized to the system clock

Keywords

CMOS integrated circuits; digital signal processing chips; phase-locked loops; 1 micron; 16-tap linear-phase transversal filtering; 20 ns; 37.5 mm; 8 bits; DCT; PLL; double-level-metal CMOS technology; eight-point discrete cosine transformation; high-speed adaptive filtering; high-speed clock; high-speed operation; instruction cycle time; micro DSP core; multiply/accumulate function; operation; programmable phase-locked loop circuit; reconfigurable high-speed data path; system clock; video-signal processing; Adaptive filters; CMOS process; CMOS technology; Circuits; Clocks; Digital signal processing; Digital signal processing chips; Digital signal processors; Filtering; Transversal filters;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.5945

Filename

5945