Title :
A 2-μm CMOS digital adaptive equalizer chip for QAM digital radio modems
Author :
Meier, S.R. ; de Man, E. ; Noll, Tobias G. ; Loibl, U. ; Klar, Heinrich
Author_Institution :
Siemens AG, Munich, West Germany
fDate :
10/1/1988 12:00:00 AM
Abstract :
The design and fabrication of a fully digital adaptive equalizer chip for QAM (quadrature amplitude modulation) digital radio modems is reported. The chip contains 107936 transistors on a silicon area of 94.6 mm2. The chip was designed in a 2-μm CMOS technology for a clock and sampling rate of 23.5 MHz. Accordingly, the functional throughput rate per chip area is 6.7 1011 eq. gates Hz/cm2. The inputs and outputs of the chip are ECL compatible, using a control unit compensating the influence of transistor parameter variations. For proper communication between chips having different technology parameters, a matched clocking scheme for synchronization was developed. A complex-valued equalizer was realized with four chips and tested in a 16-QAM digital radio modem, running at 35-MHz clock frequency
Keywords :
CMOS integrated circuits; VLSI; adaptive systems; amplitude modulation; digital integrated circuits; digital radio systems; emitter-coupled logic; equalisers; modems; 16-QAM; 2 micron; 23.5 MHz; 35 MHz; CMOS; ECL compatible; QAM digital radio modems; VLSI; clock frequency; complex-valued equalizer; digital adaptive equalizer chip; fabrication; matched clocking scheme; quadrature amplitude modulation; sampling rate; synchronization; Adaptive equalizers; CMOS technology; Clocks; Digital communication; Fabrication; Modems; Quadrature amplitude modulation; Sampling methods; Silicon; Throughput;
Journal_Title :
Solid-State Circuits, IEEE Journal of
