Title :
Balanced compensation for highly linear MOSFET gate capacitor branch
Author :
Leelavattananon, K. ; Toumazou, C. ; Hughes, J.B.
Author_Institution :
Imperial Coll. of Sci., Technol. & Med., London, UK
fDate :
8/19/1999 12:00:00 AM
Abstract :
The compatibility of the switched-capacitor technique with standard digital CMOS processes utilising MOSFET gate capacitance has recently been investigated. Owing to its high voltage-dependence, a technique for enhancing linearity which is suitable for non-delay-free circuits is proposed. The technique was verified by simulation to demonstrate its effectiveness for linearity improvement
Keywords :
CMOS digital integrated circuits; MOSFET; compensation; switched capacitor networks; balanced compensation; gate capacitor branch; highly linear MOSFET; linearity improvement; non-delay-free circuits; standard digital CMOS processes; switched-capacitor technique;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19990992
