Implementation of microprogrammed control in FPGAs

The microprogrammed approach to implementing control state machines has been widely used since the early 1960s and has the advantages of structured programming and fixed timing characteristics. This paper presents a microprogrammed control unit that has been tailored to implementation in field-programmable gate arrays (FPGAs). The microsequencer has a novel architecture which takes advantage of the enhancements existing in coarse-grained FPGAs to implement efficiently four basic functions: registers, multiplexers, adders, and counters. The sequencer supports both nested subroutines and nested loops, and can operate in both pipelined and nonpipelined modes. The pipelined mode of operation uses delayed branching in which one additional microinstruction always executes following any instruction that changes program flow. It is found that in a typical medium-sized (50 K gates) FPGA, the sequencer can be clocked at over 60 MHz nonpipelined and over 100 MHz pipelined while using less than 5% of the available FPGA logic resources. This leaves the bulk of the FPGA resources available for implementing other digital circuitry that is to be controlled by the microsequencer. While not attractive for a small number of states, the microprogrammed approach has some significant advantages for complex controllers with a large number of states