DocumentCode :
1268079
Title :
Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms
Author :
Kagaris, Dimitrios ; Tragoudas, Spyros ; Karayiannis, Dimitrios
Author_Institution :
Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
Volume :
16
Issue :
3
fYear :
1997
fDate :
3/1/1997 12:00:00 AM
Firstpage :
309
Lastpage :
315
Abstract :
Nonenumerative path-delay fault coverage estimation for combinational circuits estimates the fault coverage of a given test set without explicit enumeration of all paths in the circuit. In a recent nonenumerative method, it was proposed that a set C of lines be located in the circuit so that the set forms a cut and no lines in the set belong to the same path. Each line in the cut defines a subcircuit consisting of all paths that contain the line. Fault coverage may be obtained by working on all the subcircuits without double-counting path-delay faults. The main result of this paper is a polynomial time algorithm for finding a maximum cardinality set C. Besides its theoretical importance, our extensive experimental results on the ISCAS´85 benchmarks show that the larger the set C (and the number of subcircuits), the better the fault coverage estimation. More subcircuits may be generated only in a heuristic manner. It was proposed to consider two or more line-disjoint cuts Ci. We propose a technique where only one Ci must be a cut. This scheme is based on novel algorithms and results in more subcircuits than the previous one
Keywords :
circuit analysis computing; combinational circuits; delays; fault diagnosis; graph theory; logic testing; combinational circuits; line dependency graph; logic circuits; maximum cardinality set; nonenumerative estimation; optimal polynomial-time algorithms; path-delay fault-coverage estimation; test set; Circuit faults; Circuit testing; Combinational circuits; Computer science; Delay estimation; Electrical fault detection; Fault detection; Polynomials; Robustness; Timing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.594836
Filename :
594836
Link To Document :
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