DocumentCode
1268256
Title
Compact Modeling of a Generic Double-Gate MOSFET With Gate–S/D Underlap for Subthreshold Operation
Author
Vaddi, Ramesh ; Agarwal, R.P. ; Dasgupta, S.
Author_Institution
ECE Dept., Padmashri Dr. B.V. Raju Inst. of Technol., Hyderabad, India
Volume
59
Issue
10
fYear
2012
Firstpage
2846
Lastpage
2849
Abstract
In this brief, a new analytical model to compute the potential distribution in gate overlap and underlap regions of a generic double-gate (DG) MOSFET (valid for asymmetric features in front- and back-gate insulator thicknesses, gate bias, and gate work functions) for operation in the subthreshold condition is proposed. A closed form solution to 2-D Poisson´s equation is obtained with approximation of parabolic potential function along vertical direction of the device. Conformal mapping technique is applied for modeling fringe electric field in the underlap regions. The proposed potential model is extended in deriving important device parameters such as threshold voltage, threshold voltage rolloff, DIBL, subthreshold swing, etc. Model predictions demonstrate that significant improvement in subthreshold operation can be achieved with 4T asymmetric underlap DG MOSFETs in comparison to 3T symmetric nonunderlap DG MOSFETs.
Keywords
MOSFET; Poisson equation; electric fields; 2D Poisson equation; 3T symmetric nonunderlap DG MOSFET; 4T asymmetric underlap DG MOSFET; DIBL; asymmetric features; back-gate insulator thicknesses; closed form solution; compact modeling; conformal mapping technique; fringe electric field modeling; front-gate insulator thicknesses; gate bias; gate overlap regions; gate underlap regions; gate work functions; gate-s-d underlap; generic double-gate MOSFET; model predictions; parabolic potential function; subthreshold operation; subthreshold swing; threshold voltage rolloff; vertical direction; Analytical models; Electric potential; Logic gates; MOSFET circuits; Semiconductor device modeling; Silicon; Threshold voltage; Analytical subthreshold model; asymmetric double-gate (DG) (ADG) MOSFET; compact modeling; fringe field modeling; gate underlap; independent (4T) DG MOSFET;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2012.2208464
Filename
6275481
Link To Document