Realistic modelling of blocked packets for accurate performance evaluation of ATM switches

Author

Atiquzzaman, M. ; Chen, C.K.

Author_Institution

Dept. of Electr. & Comput. Eng., Dayton Univ., OH, USA

Volume

146

Issue

4

fYear

1999

fDate

8/1/1999 12:00:00 AM

Firstpage

213

Lastpage

221

Abstract

Multistage switches have been used as ATM switching fabrics in broadband ISDN networks, and also to connect processors to memories in massively parallel multiprocessor systems. Previous performance models for multistage switches have been neither accurate enough nor based on realistic assumptions regarding modelling the correlation of the blocked packets in successive stages of the switch. Two new analytical models for accurate analysis of multistage switches are proposed. The new models reflect the realistic behaviour of blocked packets, and take into account the fact that a blocked packet always hunts for the same output link in successive clock cycles. The results obtained from the models are more accurate than those available in the literature

Keywords

B-ISDN; asynchronous transfer mode; buffer storage; multistage interconnection networks; packet switching; probability; telecommunication network routing; ATM switches; ATM switching fabrics; analytical models; blocked packets correlation; broadband ISDN; buffer model; clock cycles; massively parallel multiprocessor systems; memories; multistage switches; output link; performance evaluation; performance models; processors; routing probabilities; state probabilities;

fLanguage

English

Journal_Title

Communications, IEE Proceedings-

Publisher

iet

ISSN

1350-2425

Type

jour

DOI

10.1049/ip-com:19990594

Filename

803781