DocumentCode :
1268951
Title :
Optimization and tolerance analysis of QCSE modulators and detectors
Author :
Neilson, David T.
Author_Institution :
Dept. of Phys., Heriot-Watt Univ., Edinburgh, UK
Volume :
33
Issue :
7
fYear :
1997
fDate :
7/1/1997 12:00:00 AM
Firstpage :
1094
Lastpage :
1103
Abstract :
This paper describes the design constraints and optimization of multiple-quantum-well (MQW) devices for use as flip-chip bonded devices on silicon circuitry. These devices act as quantum-confined Stark effect (QSCE) modulators and detectors. It is shown that the optimal device thickness depends upon the biasing voltage levels as well as the voltage swing that is available from the silicon circuitry. Lower voltages favor thinner device designs. It was found that, for GaAs-AlGaAs quantum wells, a design in which the modulator and detector are of identical design, a combined efficiency of 0.36 could be achieved with a 5-V swing on the modulators, falling to 0.21 with 2.5 V. By using separate layers for the design of the modulator and detector, the performance could be improved significantly with 0.48 achievable for a 5-V swing. It is shown that optimizing the device to minimize nonuniformity effects makes the optimal design thinner
Keywords :
III-V semiconductors; aluminium compounds; electro-optical modulation; flip-chip devices; gallium arsenide; integrated circuit interconnections; optical interconnections; optimisation; photodetectors; quantum confined Stark effect; semiconductor quantum wells; smart pixels; tolerance analysis; CMOS circuitry; GaAs-AlGaAs; GaAs-AlGaAs quantum wells; MQW devices; QCSE detectors; QCSE modulators; biasing voltage levels; combined efficiency; design constraints; flip-chip bonded devices; nonuniformity effect minimization; optical interconnections; optimal device thickness; optimization; quantum-confined Stark effect; smart pixel applications; tolerance analysis; voltage swing; Bonding; Circuits; Constraint optimization; Design optimization; Detectors; Quantum well devices; Silicon; Stark effect; Tolerance analysis; Voltage;
fLanguage :
English
Journal_Title :
Quantum Electronics, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9197
Type :
jour
DOI :
10.1109/3.594871
Filename :
594871
Link To Document :
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