Capacitance scaling based energy efficient FIR filter for digital signal processing

In this work, we are implementing FIR Gaussian low pass filter using DSP slice available in 28nm Kintex-7 FPGA. In order to make energy efficient filter, we are using capacitance scaling. During capacitance scaling, we observe that there is no change in clock power, logic power, signal power and DSP power. But, there is significant reduction in IOs power, leakage power and total power of FIR filter on 28nm Kintex-7 FPGA. There is approx 44.74% reduction in IOs power when FIR filter operating frequency is 5GHz, 50GHz, 500GHz and 1THz and capacitance is scaled down from 25pF to 5pF. There is approx 87.65% reduction in leakage power when FIR filter operating frequency is from 500GHz to 5GHz. There is approx 99.51% reduction in leakage power when FIR filter operating frequency is from 1THz to 5GHz.