Title :
A circuit-level simulation model of PNPN devices
Author :
Brambilla, Angelo ; Dallago, Enrico
Author_Institution :
Dept. of Electr. Eng., Pavia Univ., Italy
fDate :
12/1/1990 12:00:00 AM
Abstract :
A numerical model of a three-junction device is presented. It allows the simulation of the external characteristics of the PNPN family devices, and in this work the simulation of the gate turn-off thyristor is particularly considered. The reasons that led to the realization of this model are explained by reviewing previous works in this area. The model is based on the Ebers-Moll equations extended to include the three-junction devices, and it is implemented (built-up) in the source code of the SPICE2 circuit simulator. A detailed description of the implementation of the model equations and different tests are reported and discussed. The results are in accordance with the measurements from the devices reported on data sheets and the computation time is sufficiently short
Keywords :
circuit analysis computing; semiconductor device models; thyristors; Ebers-Moll equations; GTO devices; SPICE2 circuit simulator; circuit-level simulation model; gate turn-off thyristor; source code; three-junction device; Circuit simulation; Circuit testing; Computational modeling; DC-DC power converters; Delay effects; Differential equations; Numerical models; Power electronics; Thyristors; Time measurement;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
