Title :
Layer assignment for multichip modules
Author :
Ho, Jan Ming ; Sarrafzadeh, Majid ; Vijayan, Gopalakrishnan ; Wong, C.K.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
12/1/1990 12:00:00 AM
Abstract :
The layer assignment problem that arises in the design of a multichip module, a high-performance compact package for the interconnection of several hundred chips, is studied. The aim is to place each net in a x-y pair of layers, so as to minimize the number of such pairs. An approximation algorithm, running in O(nd) time is presented for minimizing the number of layers, where n is the number of nets and d is the (two-dimensional) density of the problem
Keywords :
circuit layout CAD; modules; packaging; CAD; approximation algorithm; global routeing; interconnection; layer assignment; layout design; multichip modules; package; Aging; Approximation algorithms; Delay; Joining processes; Multichip modules; Packaging machines; Pins; Routing; Very large scale integration; Wiring;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
