Using functional fault simulation and the difference fault model to estimate implementation fault coverage

An approach to estimate the fault coverage of the implementation of a VLSI design obtained by fault simulation at the function level is presented. The proposed methodology begins by defining a fault model for the functional level, the difference fault model (DFM), which reflects all of the faults in the implementation level. Functional fault detection is recorded by performing a functional simulation of the design, with faults injected as determined by the DFM. The last step is to use the correspondence between the functional faults (in the DFM) and those of the implementation level to yield an estimate of the implementation fault coverage. The results obtained show a very good correlation between the estimated fault coverage, based on fault simulation at the functional level, and the actual fault coverage obtained by fault simulation on a gate-level implementation