• DocumentCode
    1269635
  • Title

    A cone-based genetic optimization procedure for test generation and its application to n-detections in combinational circuits

  • Author

    Pomeranz, Irith ; Reddy, Sudhakar M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
  • Volume
    48
  • Issue
    10
  • fYear
    1999
  • fDate
    10/1/1999 12:00:00 AM
  • Firstpage
    1145
  • Lastpage
    1152
  • Abstract
    Test generation procedures based on genetic optimization were shown to be effective in achieving high fault coverage for benchmark circuits. In this work, we propose a representation of test patterns for genetic optimization based test generation, where subsets of inputs are considered as indivisible entities. Using this representation, crossover between two test patterns t1 and t2 copies all the values of each subset either from t1 or from t2. By keeping input subsets undivided, activation and propagation capabilities of t1 and t2 are expected to be captured and carried over to the new test patterns. Experimental results presented show that the proposed scheme results in complete stuck-at test sets and n-detection test sets for combinational circuits, even in cases where other procedures report incomplete fault coverages
  • Keywords
    combinational circuits; genetic algorithms; logic testing; combinational circuits; fault coverage; genetic optimization; n-detections; test generation; test patterns; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Genetic mutations; Test pattern generators;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.805164
  • Filename
    805164