Title :
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization
Author :
Yang, Saeyang ; Ciesielski, Maciej J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fDate :
1/1/1991 12:00:00 AM
Abstract :
A novel theoretical formulation of the input encoding problem is presented, based on the concept of compatibility of dichotomies. The input encoding problem is shown to be equivalent to a two-level logic minimization. Three possible techniques to solve the encoding problem are discussed, based on: techniques borrowed from classical logic minimization (generation of prime dichotomies and solving the covering problem); graph coloring applied to the graph of incompatibility of dichotomies; and extraction of essential prime dichotomies followed by graph coloring. The extraction of essential prime dichotomies serves the same purpose as the extraction of essential prime implicants in logic minimization, in the sense that it reduces the size of the covering/graph coloring problem. The conditions of optimality of the solutions to the input encoding problem are discussed. For near-optimum results a powerful heuristic, based on an iterative improvement technique, has been developed and implemented as a computer program: dichotomy-based symbolic input encoding technique (DIET). The test results indicate the DIET compares favorably with KISS and NOVA in terms of the CPU time, is superior to both programs in terms of the encoding length, and requires considerably less memory. This method can be applied to the input encoding of combinational logic and the state assignment of finite state machines (FSMs) in both two-level and multilevel implementations
Keywords :
combinatorial circuits; encoding; finite automata; graph colouring; iterative methods; logic CAD; minimisation of switching nets; CPU time; combinational logic; dichotomy-based symbolic input encoding; encoding length; finite state machines; graph coloring; heuristic; input encoding; iterative improvement; logic minimization; multilevel implementations; optimality; state assignment; suboptimum algorithms; two-level implementation; two-level logic minimization; Automata; Boolean functions; Central Processing Unit; Encoding; Logic; Microelectronics; Minimization methods; State feedback; Testing; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on