Title :
A 70-MHz 1.2-μm CMOS 16-point DFT processor
Author :
Linderman, Richard W. ; Shephard, Carl G. ; Taylor, Kent ; Coutee, P.W. ; Rossbach, P.C. ; Collins, James M. ; Hauser, Robert S.
Author_Institution :
US Air Force Inst. of Technol., Wright-Patterson AFB, OH, USA
fDate :
4/1/1988 12:00:00 AM
Abstract :
A chip architecture designed to compute a 16-point discrete Fourier transform (DFT) using S. Winograd´s algorithm (1978) every 457 ns is presented. The 99500-transistor 1.2-μm chip incorporates arithmetic, control, and input/output circuitry with testability and fault detection into a 144-pin package. A throughput of 2.3×1012 gate-Hz/cm2 and 79-million multiplications/s is attained with 70-MHz pipelined bit-serial logic. Combined with similar chips computing 15- and 17-point DFTs, 4080-point DFTs can be computed every 118 μs. Using the 16- and 17-point chips, 272×272-point complex data imagery can be transformed in 4.25 ms. A 24-bit block floating-point data representation combined with an adaptive scaling algorithm delivers a numerical precision of 106 dB (17.6 bits) after computing 4080-point DFTs
Keywords :
CMOS integrated circuits; Fourier transforms; VLSI; computerised picture processing; digital arithmetic; microprocessor chips; 1.2 micron; 16-point DFT processor; 24-bit block floating-point data representation; 4080-point DFTs; 457 ns; 70 MHz; ASIC; CMOS; VLSI; adaptive scaling algorithm; chip architecture; custom ICs; digital signal processing; discrete Fourier transform; fault detection; numerical precision; pipelined bit-serial logic; testability; throughput; Algorithm design and analysis; Arithmetic; CMOS process; Circuit testing; Computer architecture; Design for testability; Discrete Fourier transforms; Electrical fault detection; Packaging; Throughput;
Journal_Title :
Solid-State Circuits, IEEE Journal of
