Synchronous logic synthesis: algorithms for cycle-time minimization

Author

De Micheli, G.

Author_Institution

Comput. Syst. Lab., Stanford Univ., CA

Volume

10

Issue

1

fYear

1991

fDate

1/1/1991 12:00:00 AM

Firstpage

63

Lastpage

73

Abstract

A novel approach to logic synthesis of digital synchronous circuits is presented. A model for synchronous circuits that supports logic transformations aimed at optimizing the circuit performance is presented. Previous synthesis approaches attacked this problem by separating the combinational logic from the registers and by applying circuit transformations to the combinational component only. It is shown how to optimize concurrently the circuit equations and the register position by a set of algorithms based on logic transformations. Experimental results on benchmark circuits are reported

Keywords

combinatorial circuits; logic CAD; minimisation; performance evaluation; benchmark circuits; circuit equations; circuit transformations; combinational logic; cycle-time minimization; digital synchronous circuits; logic synthesis; logic transformations; model; register position; Circuit synthesis; Combinational circuits; Integrated circuit interconnections; Integrated circuit synthesis; Logic circuits; Logic design; Minimization methods; Network synthesis; Programmable logic arrays; Registers;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.62792

Filename

62792