Accelerating accurate fault tree analysis using HW/SW co-design

Fault tree analysis is a widespread-use method for measuring dependability parameters such as reliability and safety. Fault tree analysis is more popular than Markov modeling and Reliability Block Diagram (RBD), which need good background of mathematical equations and impose complex analysis for large systems. In this paper, accurate analysis of the fault tree is accelerated using a hardware/ software (HW/SW) co-design. This method converts a fault tree into a stochastic-based tree with logic gates and long bit streams as its inputs. This kind of tree has an exponential function and conversion of probability to a stochastic bit stream, which uses a random number generator. Moreover, based on probabilistic analysis of dynamic gate i.e., Cold Spare, an accurate model of its stochastic gate is developed. So, implementing it on a HW/SW co-design platform, speeds up the analysis as well as accuracy. The experimental results show that implementing this method on HW/SW co-design is 14 times faster than CPU implementation and 21 times more accurate than previous methods.